SEEC: Stanford Extremely Efficient Computing



Today, the non-recurring engineering costs for chip design are in the tens of millions of dollars. The masks or manufacturing costs are probably less than 10% of the total – design costs dominate the NRE. Consequence of this high cost is that only a few market segments with large volumes can justify designing an ASIC. This decrease in ASIC starts is coming at a time when technology scaling no longer provides great performance of energy improvement. Thus, unless we figure out how to create cheap application optimized chips, the overall computing performance will stop scaling. The goal of this research area is to create a new design methodology which will reduce design NRE costs by an order of magnitude. To accomplish this low design cost, we believe people should design a system to create variants of a chip rather than creating a single chip – we need to design chip generators, not chips. We are focusing our efforts on building a generator for image signal processing. We have already completed generators for chip multiprocessors, floating point units and FFTs.