Date	Author	Thesis
Jan 1984	Mark Alan Horowitz	Timing Models For MOS Circuits
Mar 1986	Peter Eichenberger	Fast symbolic layout translocation for custom VLSI integrated circuits
Oct 1988	Clyde Carpenter	Incremental VLSI Compaction
Oct 1988	Chorng-Yeong Chu	Improved Models for Switch-Level Simulation
May 1989	James A. Gasbarro	An Architecture for High-Performance Cingle-Chip VLSI Testers
Jun 1989	William M. Johnson	Super-Scalar Processor Design
Jun 1989	Michael Spreitzer	Comparing structurally different views on a VLSI design
Oct 1989	Mark Ronald Santoro	Design And Clocking Of VLSI Multipliers
Aug 1990	Ted Williams	Latency And Throughput Tradeoffs In Self-Timed Speed-Independent Pipelines And Rings
Mar 1991	Don Stark	Analysis Of Power Supply Networks In VLSI Circuits
May 1991	Ted Eugene Williams	Self-Timed Rings And Their Application To Division
Jun 1992	Mark Edward Dean	STRiP: A Self-Timed RISC Processor
Jun 1992	Russell Kao	Piecewise Linear Models For Switch-Level Simulation
Oct 1992	Richard Simoni	Cache Coherence Directories For Scalable Multiprocessors
Nov 1992	Michael David Smith	Support For Speculative Execution In High-Performance Processors
May 1993	Arturo Salz	Incremental Tools For The Design And Verification Of VLSI Circuits
Jun 1994	John George Maneatis	Precise Delay Generation Using Coupled Oscillators
Jan 1995	Drew Eric Wingard	High-Speed BiCMOS Memories
Nov 1995	Thomas Stephen Chanak	Netlist Processing For Custom VLSI Via Pattern Matching
Nov 1996	Chian-Min Richard Ho	Validation Tools For Complex Digital Designs
Jun 1997	Ricardo E. Gonzalez	Low-Power Processor Design
Apr 1998	Stefanos Sidiropoulos	High Performance Inter-Chip Signalling
Dec 1998	Chih-Kong Ken Yang	Design Of High-Speed Serial Links In CMOS
Feb 1999	David Harris	Skew-Tolerant Circuit Design
Aug 1999	Bharadwaj S. Amrutur	Design And Analysis Of Fast Low Power Srams
Aug 1999	Kun-Yung Chang	Design Of A CMOS Asymmetric Serial Link
May 2000	Hema Kapadia	Partitioning-Driven Convergence in the Design of Random-Logic Blocks
Jun 2001	Matthew Eldridge	Designing Graphics Architectures Around Scalability And Communication
Jun 2001	Gu-Yeon Wei	Energy-Efficient I/O Interface Design With Adaptive Power-Supply Regulation
Jun 2001	William F. Ellersick	Data Converters For High Speed CMOS Links
Oct 2001	James Christopher Wilson	Symbolic Simulation using automatic abstraction of internal node values
Aug 2001	Ming-Ju Edward Lee	An Efficient I/O And Clock Recovery Design For Terabit Integrated Circuits
Aug 2001	Lance Stirling Hammond	Hydra: A Chip Multiprocessor With Support For Speculative Thread-Level Parallelization
Nov 2001	Daniel K. Weinlader	Precision CMOS Receivers For VLSI Testing Applications
Jan 2002	Evelina Fai-Yee Yeung	Design Of High-Performance And Low-Cost Parallel Links
Dec 2002	Jaeha Kim	Design Of CMOS Adaptive-Supply Serial Links
Dec 2002	Jeff Solomon	Physical Design Datasets
Aug 2003	Ron Ho	On-Chip Wires: Scaling And Efficiency
Jun 2003	Brucek Khailany	The VLSI Implementation And Evaluation Of Area- And Energy-Efficient Streaming Media Processors
Dec 2003	Dean Liu	A Framework For Designing Reusable Analog Circuits
Dec 2003	David J. Lie	Architectural Support For Copy And Tamper-Resistant Software
Feb 2003	Ujval J. Kapasi	Conditional Techniques For Stream Processing Kernels
Mar 2004	Timothy John Purcell	Ray Tracing On A Stream Processor
Mar 2004	Neel S. Joshi	Color Calibration For Arrays Of Inexpensive Image Sensors
Jun 2004	Kurt Akeley	Achieving Near-Correct Focus Cues Using Multiple Image Planes
Jun 2004	Jeffrey S. Gibson	Memory Profiling On Shared-Memory Multiprocessors
May 2004	Isaac Keslassy	The Load-Balanced Router
Aug 2004	Azita Emami-Neyestanak	Design Of CMOS Receivers For Parallel Optical Interconnects
Sep 2004	Vladimir Stojanovic	Channel-Limited High-Speed Links: Modeling, Analysis And Design
Dec 2004	Robert C. Kunz	Performance Bottlenecks On Large-Scale Shared-Memory Multiprocessors
Dec 2004	Bennett Wilburn	High Performance Imaging Using Arrays Of Inexpensive Cameras
Mar 2005	Aparna Bhatnagar	Low Jitter Clocking Of CMOS Electronics Using Mode-Locked Lasers
Jun 2005	Ken Mai	Design And Analysis Of Reconfigurable Memories
Sep 2005	Nuwan S. Jayasena	Memory Hierarchy Design For Stream Computing
Sep 2005	Elizabeth Seamans	Processor Efficiency For Packet-Processing Applications
Dec 2005	Manohar Karkal Prabhu	Parallel Programming Using Thread-Level Speculation
Jul 2006	Ren Ng	Digital Light Field Photography
Sep 2006	Gaurav Garg	Efficiently Acquiring Reflectance Fields Using Patterned Illumination
Sep 2006	Augusto Roman	Multiperspective Imaging For Automated Urban Visualization
Nov 2006	Hae-Chang Lee	An Estimation Approach To Clock And Data Recovery
Dec 2006	Elad Alon	Measurement And Regulation Of On-Chip Power Supply Noise
Dec 2006	Alessandro Magnani	Primal-Dual Cutting-Plane Method For Distributed Design
Mar 2007	Vaibhav Vaish	Synthetic Aperture Imaging Using Dense Camera Arrays
Jul 2007	Patrick Chiang	Precison Clock Synthesis Using Direct Modulation Of Front-End Multiplexers/Demultiplexers In High Speed Serial Link Transceivers
Sep 2007	Samuel Palermo	Design Of High-Speed Optical Interconnect Transceivers
Sep 2007	Vicky W. Wong	Characterizing The Parallel Performance And Soft Error Resilience Of Probabilistic Inference Algorithms
Nov 2007	James Alden Weaver	Measuring Supply Currents in Printed Circuit Boards
Mar 2008	Amir Amirkhany	Multi-Carrier Signaling For High-Speed Electrical Links
Mar 2008	David Black-Schaffer	Block Parallel Programming For Real-Time Applications On Multi-Core Processors
Mar 2008	Dinesh Patil	Design Of Robust Energy-Efficient Digital Circuits Using Geometric Programming
Mar 2008	John Kim	High-Radix Interconnection Networks
Apr 2008	Jacob C. Chang	Formal Verification Along With Design For Transactional Models
Jun 2008	Francois Labonte	A Stream Virtual Machine
Aug 2008	Valentin Abramzon	Analog-To-Digital Converters For High-Speed Links
Aug 2008	Xiling Shen	Hybrid Modeling And Robustness Analysis Of Cell Cycle Regulation
Dec 2008	Amin Firoozshahian	Smart Memories: A Reconfigurable Memory System Architecture
Dec 2008	Bita Nezamfar	Energy-Performance Tunable Digital Circuits
Dec 2008	Alexandre Solomatnikov	Polymorphic Chip Multiprocessor Architecture
Feb 2009	Michael D. Linderman	A Programming Model And Processor Architecture For Heterogeneous Multicore Computers
May 2010	Fernando Amat Gil	Alignment Of Cryo-Electron Tomography Images Using Markov Random Fields
Aug 2010	Farshid Moussavi	Geometric Context Driven Inference For High Throughput Cryogenic Electron Tomography
Aug 2010	Omid Jalal Azizi	Design And Optimization Of Processors For Energy Efficiency: A Joint Architecture-Circuit Approach
Feb 2011	Eino-Ville Aleksi Talvala	The Frankencamera: Building A Programmable Camera For Computational Photography
May 2011	Ofer Shacham	Chip Multiprocessor Generator: Automatic Generation Of Custom And Heterogeneous Compute Platforms
Jul 2011	Andrew B. Adams	High-Dimensional Gaussian Filtering For Computational Photography
Aug 2011	Zhengyun Zhang	Analysis And Synthesis Of Three-Dimensional Illumination Using Partial Coherence
Dec 2011	Ray Nguyen	Dynamic Amplifiers For High-Speed Pipelined A/D Conversion
Nov 2011	Chung Chun Wan	CMOS Image Sensors With Multi-Bucket Pixels For Computational Photography
Nov 2011	Metha Jeeradit	Mixed Equation-Simulation Circuit Optimization
Mar 2012	James Chen	Self-Calibrating On-Chip Interconnects
Aug 2012	Kyle R. Kelley	High-Level Digital Interfaces With Low Overhead
Nov 2012	Sameh Galal	Energy Efficient Floating-Point Unit Design
Dec 2012	Byong Chan Lim	Model Validation Of Mixed-Signal Systems
May 2013	James Mao	Circuitbook: A Framework For Analog Design Reuse
Jun 2013	Megan A. Wachs	Specifying And Validating Memory Protocols For Chip Generators
Jul 2013	Limor Freifeld	Dissecting The Neural Circuits Of Early Visual Processing In Drosophila
Aug 2013	Frances Wing Yee Lau	Design And Development Of A 1mm Resolution Clinical Positron Emission Tomography (PET) System
Aug 2013	Krishna Teja Malladi	Energy Proportional Memory Systems
Dec 2013	Vladimir Kibardin	Synthesis Of Microfluidic Chips
Dec 2013	Wajahat Qadeer	Application Optimized Computing
Dec 2013	Rehan Hameed	Balancing Efficiency And Flexibility In Specialized Computing
Dec 2013	John Peter Stevenson	Fine-Grain In-Memory Deduplication For Large-Scale Workloads
May 2014	Sabrina Liao	Verilog Piecewise Linear Behavioral Modeling For Mixed-Signal Validation
Jul 2014	Andrew Danowitz	Exploring Abstract Interfaces In System-On-Chip Integration
Jun 2015	Zain Asgar	GPU Energy Modeling And Analysis
Oct 2018	Heonjae Ha	Understanding And Improving The Energy Efficiency Of DRAM
Mar 2019	Artem Vasilyev	Evaluating Spatially Programmable Architecture For Imaging And Vision Applications
Oct 2019	Xuan Yang	A Systematic Framework To Analyze The Design Space Of DNN Accelerators
Dec 2019	Jing Xiong	Mapping Histological Brain Images To The Allen Mouse Brain Atlas
Aug 2020	Hamid Partovi	A Scalable All Digital 64 X 48 Pixel Flash Lidar Image Sensor
Jun 2021	Steven Herbst	An Open-Source Framework For FPGA Emulation Of Analog/Mixed-Signal Integrated Circuit Designs
Jun 2021	Sung-Jin Kim	Sythesizable Mixed-Signal Building Blocks For Open Source High Speed Serial Links
Dec 2021	Amy Verkler	Stanford Circuit Debugging Simulator: A New Tool For Teaching
Aug 2022	Steven Bell	F4graph: An API For Camera Scheduling And Heterogeneous Image Processing On Mobile Devices
Dec 2022	Keyi Zhang	Source-Level Debugging For Hardware Generator Frameworks
Mar 2023	Ankita Nayak	Improving Energy Efficiency For CGRA Architectures
Sep 2023	Daniel Stanley	Fixture: A Tool For Automated Modeling Of Mixed-Signal Systems
Dec 2023	Qiaoyi Liu	Compiling Applications To Reconfigurable Push-Memory Accelerators
Dec 2023	Jeff Setter	Compiling Image Processing And Machine Learning Applications To Reconfigurable Accelerators

Notes: Click on triangles to sort columns.
For dev tools see Steve R. and/or "~steveri/webpage/mh-theses/"