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Low-Power Link Design and Modeling

Research Area: Rethinking Analog Design
The goal of this project is to build commerically feasible, low-cost, low-power, medium-speed, chip-to-chip links taking advantage of recent developments in optical technology.

As achieving such goal requires careful trade-off analysis of various parameters (e.g. speed, power, area, noise margin, etc.), the project leverages the analog design methodologies newly developed in the group: modeling, optimization, and simulation. We are currently exploring the trade-offs in a number of link architectures and circuit implementations and planning to build a low-power link test chip that demonstrate our findings.

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