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A Memory System Design Framework

Research Area: Smart memories
Status: Not started  
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Description:
The move to chip level multiprocessors (CMP), where multiple processor cores are integrated on the same die, fundamentally shifts the focus and complexity of the systems towards the memory subsystem. The memory subsystem serves as the primary means for data storage, sharing and communication that processors need to perform meaningful computations. Moreover, appearance of innovative proposals for multiprocessor memory systems, such as streaming and transactional memory, diversifies the semantics requirements that need to be provided in the memory system implementation. In this dissertation we observe that while having different semantics, all major memory models in today's multiprocessors rely on very similar hardware resources and operations at the implementation level. The different memory access semantics are generated by altering how the primitive hardware operations are composed. We propose a universal memory system architecture that implements the shared resources and exports the common operations, enabling a user to implement different memory protocols by "programming" the operations that occur in the memory system. The system consists of storage elements for storing data and state information, communication channels for performing data transfers and exchanging control messages, and associated controllers which sequencing and carry out control operations. We present Smart Memories as a concrete example of such reconfigurable memory system and discuss its architecture and hardware mechanisms that provide flexibility. We also explain how protocols can be mapped to this hardware substrate by providing a simple example. Our study shows that the performance impact of the flexible hardware mechanisms are generally small, less than 20% compared to an ideal memory system, in almost all cases across three different memory models. The impact on the physical aspects of the system is more significant, consuming 60% more dynamic power and twice the area in configurable controllers compared to controllers specialized for a specific protocol.