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Faculty Advisor

Mark Horowitz
Gates 306650-725-3707
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Research Interests: VLSI, Architecture, Biology, Microfluidics

Mark Horowitz received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Since 1984 he has been a professor at Stanford working in the area of digital integrated circuit design. While at Stanford he has led a number of processor designs including MIPS-X, one of the first processors to include an on-chip instruction cache, Torch, a statically-scheduled, superscalar processor and Flash, a flexible DSM machine. He has also worked in a number of other chip design areas including high-speed memory design, high-bandwidth interfaces, and fast floating point. In 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology.





Consulting Professors

Jaeha Kim
CIS 128650-725-6599
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Research Interests: Circuit Design, High-Speed Links, Analog/Mixed-Signal Methodologies

Jaeha Kim (S'94-M'03) received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1997, and received the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1999 and 2003, respectively. Prior to joining Stanford, he was with True Circuits, Inc. (2001~2003), Seoul National University in Korea (2003~2006), and Rambus, Inc (2006~2009). His research interests include high-speed/low-power circuit design and verification methodologies for analog and mixed-signal circuits.





Staff

Stephen Richardson
Gates 460650-724-6450
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Research Interests: Computer Architecture, Compilers, VLSI

Stephen Richardson got his PhD from Stanford a long time ago, and now he's back. In the meantime, Dr. Richardson has worked at Sun Microsystems and HP research labs, where he eventually headed up a large team of hardware-oriented computer architects. Dr. Richardson was a cofounder of MicroMagic (www.micromagic.com), a processor tool and design consulting firm. Dr. Richardson has authored several papers and patents, including a patent covering the concept of multiplication by zero and one (US patent 5262973). If you multiply a number by zero and get zero as a result, you owe me a dime.




Ofer Shacham
Gates 320(650) 725-3657
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Research Interests: Computer Architecture, VLSI design

Ofer is a PhD student at Stanford University’s EE department. His fields of research, under the advisory of Prof. Mark Horowitz, include Parallel Computer Architectures, ASIC design and verification, and High Performance Computing. He holds a Masters in Electrical Engineering from Stanford University and a Bachelors in Electrical Engineering and Computer Science from Tel-Aviv University. Prior to coming to Stanford, Ofer was working at IBM Labs in Israel, on ASIC design and verification, for high performance computing. Ofer's experience also includes 5 years of active service in an elite Israeli Navy unit.




Jim Weaver
Gates 320650-714-3600
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Research Interests: Microfluidics, efficient design of power distribution networks, high frequency interconnect design.





Current Students

Zain Asgar
Gates 322650-644-9532
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Research Interests: Computer Architecture, VLSI, Graphics

Zain Asgar received his undergraduate degrees in Electrical and Computer Engineering at the University of Minnesota with Summa Cum Laude and High Distinction. He is currently pursuing his PhD under Prof. Mark Horowitz at Stanford University in the area of multiprocessors. He has worked at PMC-Sierra working on ASIC design. He is currently working at NVIDIA Corporation on the design of next generation graphics processors.




Limor Bursztyn
Gates 448
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Research Interests: Signal processing, neuroscience.

Limor Bursztyn is interested in both Electrical Engineering (with an emphasis on signal processing) and Neuroscience. She is currently involved in the Massively Parallel Brain Imaging project, led by Prof. Mark Schnitzer. In this project, a system that will enable performing two-photon imaging in 100 fruit flies (Drosophila) simultaneously is being designed. With the help of consulting Prof. Don Stark, Limor is working on the data acquisition, control and interface parts of the system. Limor has also been working with Prof. Thomas Clandinin (Neurobiology), on developing statistical signal processing techniques for using the acquired data to infer how the fly brain analyzes visual stimuli and uses the information to modulate behavior. Limor's PhD studies are funded by a Fulbright Science and Technology fellowship. Prior to starting her PhD in EE at Stanford, she received a BSc and MSc in Biomedical Engineering from Tel-Aviv University.




Andrew Danowitz
Gates 312
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Research Interests: VLSI, CAD, Architecture

Andrew Danowitz received his B.S. in General Engineering from Harvey Mudd College in May 2008. He has been working with Mark Horowitz as a Ph.D. student since 2009. Andrew's research focuses on reconfigurable hardware design in the Chip Generator project.




Sameh Galal
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Research Interests: VLSI, low power design, floating point units and computer architecture.

Sameh Galal: received BS in electronics engineering and computer science from the American university in Cairo, MS in electrical engineering from Stanford University where he is currently pursuing PhD. His research interests include: VLSI, low power design, floating point units and computer architecture.




Metha Jeeradit
Gates 318
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Research Interests: Circuit design, VLSI

Metha received his BS and MEng in Electrical and Computer Engineering from Cornell University in 2001 and 2002 respectively. He started his PhD program at Stanford in Fall 2002 before working at Rambus between 2004-2008 designing circuits for high speed links and working on circuit design methodologies. He is now working with Prof. Horowitz under the RAD initiative focusing on circuit optimization area.




Kyle Kelley
Gates 320
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Research Interests: Computer Architecture, VLSI, CAD, Convex Optimization, Finance

Kyle is a PhD candidate in Electrical Engineering at Stanford University. His research interests include energy-efficient VLSI design, parallel computing, convex optimization, machine learning, and algorithmic finance. Kyle has a BS in engineering and a BA in economics from Harvey Mudd College, and an MS in electrical engineering from Stanford University.




Frances Lau
Alway Building, Room M001(650)498-4325
This e-mail address is being protected from spambots. You need JavaScript enabled to view it http://www.stanford.edu/~flau/
Research Interests: system design, circuit design, VLSI, biomedical applications

Frances is interested in applying techniques from circuit design and VLSI to the design of biomedical systems. She is currently focusing on molecular imaging, working on the development of a breast cancer imaging PET (positron emission tomography) system. This project is done in collaboration with the Molecular Imaging Instrumentation Lab at Stanford. She is also designing a mixed-signal integrated circuit for PET applications, utilizing some of the design methodologies under the Rethinking Analog Design initiative. She completed her BASc in EE at the University of Toronto in 2005 and her MS in EE at Stanford in 2007, and is now an EE PhD candidate at Stanford.




Sabrina Liao
Gates 448
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Research Interests: analog/mixed-signal circuit design, optoelectronics, high speed links, design methodologies

Sabrina is a PhD candidate in the Stanford VLSI Group. She received her B.A.Sc in Engineering Science (EE option) from the University of Toronto in 2008 and her MSEE from Stanford University in 2009. Prior to coming to Stanford, Sabrina has had research experience in areas of multimedia communication, quantum mechanics and DCO design. In addition, she has worked at Gennum Corporation's Snowbush IP Division on ASIC verification and testing. In the summer of 2010, she interned at TI's Kilby Research Lab designing 10GHz baseband circuits for a THz communication system. Her research interests include analog/mixed-signal circuit design, optoelectronics and CMOS integration, high speed links and design methodologies. She is currently working on a high performace A/D converter design using novel design methodologies.




Byong Chan Lim
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Research Interests: Mixed-signal design methodology, mixed-signal circuits like high-speed I/O and clock recovery circuits

I received B.S. and M.S. degrees in electronic engineering from Hanyang University, Seoul, Korea, in 1997 and 2002, respectively. I am currently working toward the Ph. D. degree in electrical engineering at Stanford University. From 2003 to 2007, I had been working on analog IP developement for LG electronics.




Krishna Malladi
Gates 312
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Research Interests: Computer Architecture, Energy Efficiency in Datacenters, VLSI.

Krishna Malladi graduated from IIT Kanpur, India in 2009 with a Dual Degree (Bachelors and Masters) in Electrical Engineering with Academic-proficiency medal. Since 2009-fall, he has been a PhD student at Stanford University under the guidance of Prof. Mark Horowitz and is supported by Benchmark Capital Stanford Graduate Fellowship. His research focuses on developing Energy-efficient server architectures and memories for datacenters. He has been associated with Google and Qualcomm as an intern in 2010 and 2008 respectively. Krishna enjoys traveling, playing piano and cricket.




Kahye Song
Gates 330
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Research Interests: Statistical signal processing, image processing, computer vision, machine learning, optimization and their biomedical imaging applications such as electron tomography.

Kahye Song is a Ph.D. student at Electrical Engineering department at Stanford University. She received her BS in Electrical Engineering from Seoul National University in 2003 and MS in Electrical Engineering from Royal Institute of Technology in 2003 and also from Stanford University in 2006. She is currently working on enhancing image quality and developing image analysis tools for electron tomography. She worked for AOL advertising as a principal research engineer developing online advertising engine prior to her Ph.D. studies.




Pete Stevenson
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Research Interests: design tools for digital circuits

Pete is a Ph.D. student at Stanford University working in the field of circuit design, under the direction of professor Mark Horowitz. He aspires to develop innovative design tools for digital circuits. He is interested in closing the gap between a design implemented by HDL synthesis and a design optimized by exhaustive customization. Hailing from Tulsa, OK, Pete attended the U.S. Naval Academy from 1996 to 2000. After being commissioned as an officer in the U.S. Navy, he attended Stanford to obtain an MSEE (2002). Following this, he served on board a nuclear powered submarine, the USS Los Angeles (SSN-688) stationed in Pearl Harbor, Hawaii. Subsequent to the tour at sea, Pete taught a basic network analysis class and an introduction to communications systems class at the U.S. Naval Academy, from 2006 to 2008. Pete is married and lives with his wife, Siejen, in Menlo Park, CA. His hobbies include surfing, golf, and reading.




Megan Wachs
Gates 320
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Research Interests: VLSI design and verification, and parallel architectures

Megan Wachs has been a MS/PhD student at Stanford since 2005. Her research interests include VLSI design and verification, and parallel architectures. In 2006 she started helping with the verification of the Stanford Smart Memories CMP, and is now working on the Chip Generator Project. She has worked as an intern at Cryptography Research, Inc, in San Francisco, as well as at Celestica, Shanghai. She received her BS from Brown University in 2005 in Electrical Engineering.




Gordon Wan
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Research Interests: CMOS Image Sensor, Digital Imaging, Solid-State Devices, Signal Processing, and Linear Algebra.

Gordon received his BS in Electrical Engineering and Mathematics from the University of Texas at Austin in 2005, and his MS in Electrical Engineering from Stanford University in 2007. He is currently a PhD candidate under Prof. Mark Horowitz at Stanford University. He has received the James F. and Mary Lynn Gibbons Fellowship, the Stanford Graduate Fellowship, and the Pan Wen Yuan Scholarship. He ranked 2nd in Stanford PhD Qualifying Exam. His research interest is in CMOS image sensor, digital imaging, and solid-state devices.





Alumni

NameThesisEmail
Valentin AbramzonAnalog-to-digital converters for high-speed links This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Elad AlonMeasurement and Regulation of On-Chip Power Supply Noise This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Fernando AmatStatistical Image Processing for High-Throughput Cryo-Electron Microscope Tomography of Whole Cells This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Amir Amirkhany This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Bharadwaj AmruturDesign and Analysis of Fast Low Power SRAMs
Omid AziziDesign and Optimization of Processors for Energy Efficiency: A Joing Architecture-Circuit Approach This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Jules Bergmann
Tom ChanakNetlist Processing for Custom VLSI via Pattern Matching This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Kun-Yung ChangDesign of a CMOS Asymmetric Serial Link This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Han Chen This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Mark DeanSTRIP: A Self-Timed RISC Processor This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Bill EllersickData Converters for High Speed CMOS Links This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Azita Emami-NeyestanakDesign of CMOS Receivers for Parallel Optical Interconnects This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Amin FiroozshahianSmart Memoires: A Reconfigurable Memory System Architecture This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Jim GasbarroArchitecture for High-Performance Single-Chip VLSI TestersRambus
Ricardo GonzalezLow-Power Processor Design This e-mail address is being protected from spambots. You need JavaScript enabled to view it
David HarrisSkew-Tolerant Circuit Design This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Ron HoOn-Chip Wires: Scaling and EfficiencySun Labs
Richard HoValidation Tools for Complex Digital Designs This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Mike JohnsonSuper-Scalar Processor DesignAMD
Russell KaoPiecewise Linear Models for Switch-Level SimulationSun Labs
Hema KapadiaPartitioning-Driven Convergence in the Design of Random-Logic Blocks This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Jaeha KimDesign of CMOS Adaptive-Supply Serial Links This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Francois LabonteA Stream Virtual Machine This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Hae-Chang LeeAn estimation approach to clock and data recovery This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Ben Lee This e-mail address is being protected from spambots. You need JavaScript enabled to view it
David LieArchitectural Support for Copy and Tamper-Resistant Software This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Dean LiuA Framework for Designing Reusable Analog Circuits This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Ken MaiDesign and Analysis of Reconfigurable Memories This e-mail address is being protected from spambots. You need JavaScript enabled to view it
John ManeatisPrecise Delay Generation Using Coupled Oscillators This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Farshid MoussaviGeometric Context Driven Inference for High Throughput Cryogenic Electron Tomography This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Bita NezamfarEnergy-performance tunable circuits This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Samuel PalermoDesign of High-Speed Optical Interconnect Transceivers This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Arturo SalzIncremental Tools for the Design and Verification of VLSI Circuits
Mark SantoroDesign and Clocking of VLSI Multipliers This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Stefanos SidiropoulosHigh Performance Inter-Chip SignallingAeluros
Rich SimoniCache Coherence Directories for Scalable Multiprocessors This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Mike SmithSupport for Speculative Execution in High-Performance Processors This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Alex SolomatnikovPolymorphic Chip Multiprocessor Architecture This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Jeff SolomonThe ChipMap: Visualizing Large VLSI Physical Design Datasets This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Don StarkAnalysis of Power Supply Networks in VLSI CircuitsAeluros
Vladimir StojanovicChannel Limited High-Speed Links: Modeling, Analysis and Design This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Eino-Ville Talvala This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Jim WeaverMeasuring supply currents in printed boards This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Gu-Yeon WeiEnergy-Efficient I/O Interface Design with Adaptive Power-Supply Regulation This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Dan WeinladerPrecision CMOS Receivers for VLSI Testing Applications This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Bennet WilburnHigh Performance Imaging Using Arrays of Inexpensive Cameras This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Ted WilliamsSelf-Timed Rings and their Application to Division This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Drew WingardHigh-Speed BiCMOS Memories This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Vicky WongCharacterizing the Parallel Performance and Soft Error Resilience of Probabilistic Inference Algorithms This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Last Updated on Monday, 14 December 2009 17:56  

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