|Type of Publication:||In Proceedings||Keywords:||Datacenters, Memory, Architecture|
|Editor:||39th IEEE/ACM International Symposium on Computer Architecture (ISCA)|
To increase data center energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3× the energy per bit transferred compared to the energy consumed by a system with fully utilized memory bandwidth. Unfortunately, many data center applications stress memory capacity and latency but not bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit transferred and more efficient idle modes. We demonstrate 3-5× lower memory power, as well as better proportionality. While we target specific workloads, like web search and distributed memory caching, our comprehensive evaluation shows small performance penalties for a wide range of applications.