|Research Area:||Rethinking Analog Design|
Many mixed-signal systems use digital correction or adaptation loops to compensate non-idealities and improve performance of analog circuits, which poses challenges in validating them. For functional validation, one wants to run a large number of test vectors. But the simulation is typically very slow because the analog parts require accurate, fine-step simulation whereas the digital parts add a large number of devices. To cope with this problem, designers write high-level functional models of the analog components. These models run fast enough to check if all the operating modes of the system work properly or if the digital correction loops stabilize to the correct points, which may take over hundreds of thousands of cycles.
One the other hand, the use of functional models for analog components creates a new problem: validating that the functional model matches the circuit implementation. Occasionally, which is too often, chip failures are due to these correspondence error; systems that are validated using models are in fact non-functional with actual circuits. In most cases, the errors are mostly the trivial wiring mistakes such as mislabeled pins, inverted signals, and mismatch in bus-encoding styles. It is understandable, since the systems would not have been validated in the first place if the models had more serious functional discrepancies.
This project focuses on developing a validation methodology to check consistency between the circuit and model across all possible input patterns.