|Research Area:||Rethinking Digital Design|
Heterogeneous multicore systems hold the prospect of high energy efficiency, but are expensive to design, and often need to be customized for a particular application class. We propose to reduce the design cost by creating a “chip generator”: a flexible, parameterized virtual device which can be tailored for each specific application. With a chip generator, the design process consists of configuring system parameters at a relatively high level based on the results of running the recompiled application on the modified target hardware. The application expert uses this process to tune both the algorithm and the hardware jointly to yield maximum performance. Once the tuning process is done, the generator creates the physical design and validation suite for the application optimized design. Like many solutions in computer science, is to add a level of indirection. We plan to create a virtual configurable multiprocessor, which can be optimized for the specific requirements of each set of applications, even to the point of adding some small amounts of application specific hardware. As application developers change chip parameters, the system would reconfigure and work to re-optimize the design, providing interactive feedback on the area/performance/energy implications of design choices. When the application designers have tuned their software and the hardware it runs on, the system would then generate the chip with little manual intervention.
First we seek to better understand why ASICs are so much more efficient than processors. What are the specific mechanisms that they use, and can these be copied to make our multiprocessors more efficient. The most interesting question is how custom tuned each of these mechanisms is, since we would like to evaluate the value of customization.
The next major challenge this research will address is creating the flexible platforms that this design style requires, focusing initially on how to specify the configurable substrate at the logical/functional level. In other words, how do we actually build a chip generator?
One of the critical tasks in building a generator is to determine, given the parameters at a higher level of abstraction, how to set the parameters of the lower-level modules. While some of this task will be very application specific, there is also the generic task of finding the parameters that “optimize” the performance of the unit, along the axes that are important to the higher level module (power, throughput, latency, area). The designer may seek to maximize performance within a power budget, as is the case for high performance chips; to minimize power consumption while meeting some performance target, as is the case for embedded devices; or to optimize some other combination of requirements on performance, power and/or area. Given the importance and universality of this type of optimization, it is a critical part of our chip generation research.
We do not expect to produce a bug-free generator, and we doubt that anyone would believe us if we asserted that we had created such a thing. Therefore, an essential aspect of this research is enabling the validation of the generated designs. We do not expect our tool to automatically validate the generated designs, but we do expect it to automatically generate what we already use: testbenches, test vectors, assertions, and reference models.Internal Chip Generator Wiki