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# Title Authors Year Type of Publication
 
Results 176 - 200 of 203
0 Evaluation of charge recovery circuits and adiabatic switching for low power CWWW-VLSI design T. Indermaur, M. Horowitz 1994 article
1 A CWWW-VLSIs 500 Mbps/pin synchronous point to point link interface S. Sidiropoulos, Chih-Kong Ken Yang, M. Horowitz 1994 article
2 Self-timed logic using current-sensing completion detection M. Dean, D. Dill, M. Horowitz 1994 article
3 Precise delay generation using coupled oscillators J. Maneatis, M. Horowitz 1993 article
4 Precise delay generation using coupled oscillators J. Maneatis, M. Horowitz 1993 article
5 Circuit techniques for large CSEA SRAMs D. Wingard, D. Stark, Mark Horowitz 1992 article
6 Efficient superscalar performance through boosting M. Smith, M. Horowitz, M. Lam 1992 article
7 Efficient moment-based timing analysis for variable accuracy switch-level simulation R. Kao, M. Horowitz 1992 article
8 A zero-overhead self-timed 160-nS 54-b CWWW-VLSI divider T. Williams, M. Horowitz 1991 article
9 A zero-overhead self-timed 160ns 54b CWWW-VLSI divider T. E. Williams, M. Horowitz 1991 article
10 Tracing with Pixie M. D. Smith 1991 article
11 A 4-ns BiCWWW-VLSI translation-lookaside buffer L. Tamura, T. Yang, D. Wingard, M. Horowitz, B. Wooley 1990 article
12 Bipolar circuit elements providing self-completion-indication T. Williams, M. Horowitz 1990 article
13 A single-chip, functional tester for VLSI circuits J. Gasbarro, M. Horowitz 1990 article
14 A 3.5ns, 1W, ECL register file M. Horowitz, M. Slamowitz, B. Rose, M. Johnson 1990 article
15 A 4nS BiCWWW-VLSI translation lookaside buffer L. Tamura, T. Yang, D. Wingard, M. Horowitz, B. Wooley 1990 article
16 Boosting beyond static scheduling in a superscalar processor M. Smith, M. Lam, M. Horowitz 1990 article
17 Integrated pin electronics for VLSI functional testers J. Gasbarro, M. Horowitz 1989 article
18 SPIM: A pipelined 64x64b iterative multiplier M. Santoro, M. Horowitz 1989 article
19 A single-ended BiCWWW-VLSI sense circuit for digital circuits G. Rosseel, M. Horowitz, R. Dutton, R. Cline 1989 article
20 Limits on multiple instruction issue M. D. Smith, M. Johnson, M. Horowitz 1989 article
21 A 4-ns 4K*1-bit two-port BiCWWW-VLSI SRAM T. Yang, M. Horowitz, B. Wooley 1988 article
22 A pipelined 64x64b iterative array multiplier M. Santoro, M. Horowitz 1988 article
23 A 32 b microprocessor with on-chip 2 Kbyte instruction cache Mark Horowitz, John Hennessy, Paul Chow, P. Gulak, John Acken, Anant Agarwal, C. Chu, Scott McFarling, Steve Przybylski, Stephen Richardson, Arturo Salz, Richard Simoni, Don Stark, Peter Steenkiste, Steve Tjiang, Malcolm Wing 1987 article
24 A single-chip functional tester J. Miyamoto, M. Horowitz 1987 article