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# Title Authors Year Type of Publication
 
Results 151 - 175 of 203
0 A 0.6um CWWW-VLSI 4Gb/s transceiver with data recovery using oversampling C.-K. K. Yang, R. Farjad-Rad, M. Horowitz 1997 article
1 A semi-digital DLL with unlimited phase shift capability and 0.8-400MHz operating range S. Sidiropoulos, M. Horowitz 1997 article
2 A 2 Gb/s asymmetric serial link for high-bandwidth packet switches K. K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, M. Horowitz, N. McKeown, M. Izzard 1997 article
3 A semidigital dual delay-locked loop S. Sidiropoulos, M. Horowitz 1997 article
4 Tiny Tera: a packet switch core N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, M. Horowitz 1997 article
5 Skew-tolerant domino circuits D. Harris, M. Horowitz 1997 article
6 Skew-tolerant domino circuits D. Harris, M. Horowitz 1997 article
7 Circuit techniques for 1.5v power supply flash memory N. Otsuka, M. Horowitz 1997 article
8 A low power switching power supply for self-clocked systems G.-Y. Wei, M. Horowitz 1996 article
9 Energy dissipation in general purpose microprocessors R. Gonzalez, M. Horowitz 1996 article
10 A 50% noise reduction interface using low-weight coding K. Nakamura, M. Horowitz 1996 article
11 A CWWW-VLSI 2.5Gb/s oversampling receiver for serial links C.-K. Yang, M. Horowitz 1996 article
12 Tiny Tera: A packet switch core N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, M. Horowitz 1996 article
13 A 700 Mbps/pin CWWW-VLSI signalling interface using current integrating receivers S. Sidiropoulos, M. Horowitz 1996 article
14 A 0.8um CWWW-VLSI 2.5Gb/s oversampling receiver and transmitter for serial links C.-K. Yang, M. Horowitz 1996 article
15 Optimization of hybrid JJ/CMOS memory operating temperatures D. Gupta, B. Amrutur, E. Terzioglu, U. Ghoshal, M. Beasley, M. Horowitz 1996 article
16 Validation coverage analysis for complex digital designs Ron Ho, Mark Horowitz 1996 article
17 Clustered voltage scaling technique for low-power design K. Usami, M. Horowitz 1995 article
18 Energy dissipation in general purpose processors R. Gonzalez, M. Horowitz 1995 article
19 Current integrating receivers for high speed system interconnects S. Sidiropoulos, M. Horowitz 1995 article
20 Array-of-arrays architecture for parallel floating point multiplication H. Kapadia, Mark Horowitz, K. Falakshashi 1995 article
21 Regenerative feedback repeaters for programmable interconnections I. Dobbelaere, M. Horowitz, A. El Gamal 1995 article
22 Architecture validation for processors R. Ho, C-H. Yang, Mark Horowitz, D. Dill 1995 article
23 Techniques to reduce power in fast wide memories B. Amrutur, M. Horowitz 1994 article
24 Low-power digital design M. Horowitz, T. Indermaur, R. Gonzalez 1994 article

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