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Mark Horowitz

Personal Information:

Position:	Not specified
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Research Area:	Uncategorized


Publications:
Towards energy-proportional datacenter memory with mobile DRAM Rethinking DRAM Powermodes for Energy-Proportionality Intermediate Representations for Controllers in Chip Generators Latency Sensitive FMA Design Energy-Efficient Floating-Point Unit Design Understanding Sources of Inefficiency in General-Purpose Chips The Frankencamera: an experimental platform for computational photography Analog signal multiplexing for PSAPD-based PET detectors: simulation and experimental validation Subtomogram alignment by adaptive Fourier coefficient thresholding Alignment of Cryo-Electron Tomography Datasets Analysis of Intact Surface Layer of Caulobacter crescentus by Cryo-Electron Tomography 3D segmentation of cell boundaries from whole cell cryogenic electron tomography volumes An efficient test vector generation for checking analog/mixed-signal functional models Fortifying analog models with equivalence checking and coverage analysis Using a Configurable Processor Generator for Computer Architecture Prototyping A Memory System Design Framework: Creating Smart Memories Smart Memories Polymorphic Chip Multiprocessor Architecture and inherent robustness of a bacterial cell-cycle control system Markov random field based automatic image alignment for electron tomography Verification of Chip Multiprocessor Memory Systems Using a Relaxed Scoreboard Processor Performance Modeling using Symbolic Simulation Area-Efficiency in CMP Core Design: Co-Optimization of Microarchitecture and Physical Design Comparative evaluation of memory models for chip multiprocessors A 24Gb/s Software Programmable Multi-Channel Transmitter Chip Multiprocessor Generator Comparing memory systems for chip multiprocessors Robust Energy-Efficient Adder Topologies Automatic alignment of low SNR images: an application to cryo-ET whole cells Smart memories: A configurable processor architecture for high productivity parallel programming The Stream Virtual Machine Burst Mode Packet Receiver using a Second Order DLL CWWW-VLSI Tranceivers with Baud Rate Clock recovery for Optical Interconnects Using Texture Mapping with Mipmapping to Render a VLSI Layout Smart Memories: A Modular Reconfigurable Architecture A 32x32 CWWW-VLSI crossbar chip using asymmetric serial links The limits of electrical signalling Validation coverage analysis for complex digital designs Architecture validation for processors Array-of-arrays architecture for parallel floating point multiplication Circuit techniques for large CSEA SRAMs MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache A 32 b microprocessor with on-chip 2 Kbyte instruction cache [View All]

Projects:
A Memory System Design Framework Polymorphic Chip Multiprocessor Architecture A Stream Virtual Machine Chip Generator

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