Stanford VLSI Group Homepage

  • Increase font size
  • Default font size
  • Decrease font size
Home Chips

Chips

Monday, 17 November 2008 23:01 shacham
E-mail Print PDF
(To modify this, you need access to the database. See wiki)
2009
Smart Memories - An 8 core reconfigurable memory system processor
People:
Zain Asgar, Han Chen, Amin Firoozshahian, Rehan Hameed, Christos Kozyrakis, Wajahat Qadeer, Stephen Richardson, Ofer Shacham, Alex Solomatnikov, Don Stark, Megan Wachs, Mark Horowitz
Relevant Papers:
2005
On-chip Supply Grid Characterization w/Energy-Delay Optimal Adders
People:
Elad Alon, Valentin Abramzon, Bita Nezamfar with Radu Zlatanovici and Prof. Nikolic from UC Berkeley
Relevant Papers:
2004
CMOS Transceivers with Baud Rate Clock recovery for Optical Interconnects
People:
Azita Emami-Neyestanak
Relevant Papers:

A. Emami-Neyestanak, S. Palermo, H. Lee and M. Horowitz.CMOS Tranceivers with Baud Rate Clock recovery for Optical Interconnects. IEEE symposium on VLSI Circuits, June 2004, pages 410-413.

Reconfigurable Memory Block
People:
Ken Mai
Relevant Papers:

K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, and M. Horowitz.Architecture and Circuit Techniques for a Reconfigurable Memory Block. ISSCC, February 2004.

Power Supply Noise Measurements on the Montecito Processor
People:
Elad Alon visting HP/Intel in Ft. Collins, CO
Relevant Papers:

S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz., invited to IEEE Journal of Solid-State Circuits, Jan. 2006.

PLL Regulator and Power Supply Noise Measurements on a FlexIO Test Chip
People:
Elad Alon, Valentin Abramzon, with Rambus, Inc.
Relevant Papers:

E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, , submitted to IEEE Journal of Solid-State Circuits

V. Abramzon, E. Alon, B. Nezamfar, and M. Horowitz, Scalable Circuits for Supply Noise Measurement, submitted to IEEE European Solid-State Circuits Conference, Sept. 2005

Burst Mode Packet Receiver using a Second Order DLL
People:
Haechang Lee
Relevant Papers:

Haechang Lee, Chi Ho Yue, Samuel Palermo, Kenneth W. Mai, and Mark Horowitz.Burst Mode Packet Receiver using a Second Order DLL. IEEE Symposium on VLSI Circuits, June 2004.

2003
An Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equaltion and Data Recovery, and Power Supply Noise Measurements
People:
Vladimir Stojanovic, Elad Alon with Rambus, Inc.
Relevant Papers:

V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, G. Tsang, E. Alon, R. Kollipara, C. Werner, J. Zerbe, and M.A. Horowitz. Autonomouc Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equaltion and Data Recovery. IEEE Journal of Solid-State Circuits, April 2005.

E. Alon, V. Stojanovic, and M.A. Horowitz. Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise. IEEE Journal of Solid-State Circuits, April 2005.

V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M.A. Horowitz. Adaptive Equalization and Data Recovery in a Dual-Mode (PAM2/4) Serial Link Transceiver. IEEE Symposium on VLSI Circuits, June 2004.

A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M.A. Horowitz. Common-mode Backchannel Signaling System for Differential High-Speed Links. IEEE Symposium on VLSI Circuits, June 2004.

E. Alon, V. Stojanovic, and M. Horowitz.Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise. IEEE Symposium on VLSI Circuits, June 2004.

Low Swing Interconnect
People:
Ron Ho
Relevant Papers:

R. Ho, K. Mai, M. Horowitz. Efficient On-Chip Global Interconnects. IEEE Symposium on VLSI Circuits, June 2003.

2002
Adaptive Supply Serial Links with Sub-1V Operation and Per-Pin Clock Recovery
People:
Jaeha Kim
Relevant Papers:
J. Kim and M. A. Horowitz. Adaptive Supply Serial Links with Sub-1V Operation and Per-Pin Clock Recovery. ISSCC 2002, February 2002.
A Novel Low Power Receiver for High-Speed Optical Interconnects
People:
Azita Emami
Relevant Papers:
A. Emami-Neyestanak , D. Liu, G. Keeler, N. Helman, M. Horowitz. A 1.6 Gbps, 3mW CMOS Receiver for Optical Communication IEEE Symposium on VLSI Circuits, June 2002, pages 84-87.
2001
Adaptative power supply regulator
People:
Jaeha Kim
Relevant Papers:
J. Kim and M. A. Horowitz. An Efficient Digital Sliding Controller for Adaptive Power-Supply Regulation. Journal of Solid-State Circuits, May 2002.

J. Kim and M. Horowitz. An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation. IEEE Symposium on VLSI Circuits, June 2001, pages 133-136.

2000
Multi-Level Signalling
People:
Bill Ellersick, Ken Yang, Vladimir Stojanovic, and Siamak Modjtahedi.
Relevant Papers:
Bill Ellersick, Ken Yang, Vladimir Stojanovic, and Siamak Modjtahedi. Overview
Timing Analyzer
People:
D. Weinlader, R. Ho, C.-K. Yang, and M. Horowitz.
Relevant Papers:
D. Weinlader, R. Ho, C.-K. Yang, and M. Horowitz. An Eight Channel 36GSample/s CMOS Timing Analyzer. IEEE International Solid-State Circuits Conference, February 2000, pages 170-171.
Bandwidth Tracking PLL
People:
Stephanos Sidiropoulos and Dean Liu
Relevant Papers:
S. Sidiropoulos, D. Liu, J. Kim, G. Wei, M. Horowitz. Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers. IEEE Symposium on VLSI Ciruits, June 2000, pages 124-127.
Variable Frequency I/O
People:
Gu-Yeon Wei, Jaeha Kim, and Dean Liu
Relevant Papers:
G. Wei, J. Kim, D. Liu, S. Sidiropoulos, M. Horowitz. A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation. IEEE Journal of Solid-State Circuits, November 2000, pages 1600-1610. G-Y. Wei, J. Kim, D. Liu, S. Sidropoulos, M. Horowitz. A variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation IEEE International Solid State Circuits Conference, February 2000, pages 298-299.
Bidirectional parallel link with per pin skew compensation
People:
Evelina Yeung
Relevant Papers:
E. Yeung, M. Horowitz. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation. Journal of Solid State Circuits, November 2000, pages 1619-1628.E. Yeung, M. Horowitz. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation IEEE International Solid State Circuits Conference, February 2000, pages 256-257.
1999
32x32 Crossbar using asymmetric serial links
People:
K.-Y. K. Chang, S. Chuang, N. McKeown, M. Horowitz.
Relevant Papers:
K.-Y. K. Chang, S. Chuang, N. McKeown, M. Horowitz. A 32x32 CMOS crossbar chip using asymmetric serial links. IEEE Symposium on VLSI Circuits, June 1999.
Gad: 4-bit 12-GSamples/sec A/D converter
People:
W. Ellersick, C.-K. K. Yang, M. Horowitz, W. Dally.
Relevant Papers:
W. Ellersick, C.-K. K. Yang, M. Horowitz, W. Dally. GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link. IEEE Symposium on VLSI Ciruits, June 1999.
1998
Low Power SRAM Using Half-Swing Pulse Mode
People:
K. Mai, T. Mori, B. Amrutur, R. Ho, B. Wilburn, M. Horowitz.
Relevant Papers:
K. Mai, T. Mori, B. Amrutur, R. Ho, B. Wilburn, M. Horowitz. Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques. IEEE Journal of Solid-State Circuits, November 1998, pages 1659-1671.T. Mori, B. Amrutur, K. Mai, M. Horowitz, I. Fukushi, T. Izawa, S. Mitarai. A 1V 0.9mW at 100MHz 2k*16b SRAM utilizing a half-swing pulsed decoder and write-bus architecture in 0.25um dual-Vt CMOS. IEEE International Solid State Circuits Conference, February 1998, pages 354-355.
10 Gbps Transmitter
People:
R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, T. Lee.
Relevant Papers:
R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, T. Lee. A 0.4-um CMOS 10-Gb/s 4-PAM pre-emphasis serial link tranmitter. IEEE Symposium on VLSI Circuits, June 1998. R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, T. Lee. A 0.4-um CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE Journal of Solid-State Circuits, May 1999, pages 580-585.
Asymmetric Serial Link
People:
K. K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, M. Horowitz.
Relevant Papers:
K. K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, M. Horowitz. A 2 Gb/s/pin CMOS asymmetric serial link. VLSI Circuits Symposium, June 1998, pages 216-217.K. K.-Y. Chang, W. Ellersick, T.-S. Chuang, S. Sidiropoulos, M. Horowitz, N. McKeown, and M. Izzard. A 2 Gb/s asymmetric serial link for high-bandwidth packet switches. Hot Interconnects, August 1997, pages 171-179.
1997
Transceiver with data recovery using oversampling
People:
C.-K. K. Yang, R. Farjad-Rad, M. Horowitz.
Relevant Papers:
C.-K. K. Yang, R. Farjad-Rad, M. Horowitz. A 0.6um CMOS 4Gb/s transceiver with data recovery using oversampling. IEEE Symposium on VLSI Circuits, June 1997, pages 71-72.
Semi-Digital DLL
People:
S. Sidiropoulos and M. Horowitz.
Relevant Papers:
S. Sidiropoulos and M. Horowitz. A semidigital dual delay-locked loop. IEEE Journal of Solid-State Circuits, November 1997, pages 1083-1092.S. Sidiropoulos and M. Horowitz. A semi-digital DLL with unlimited phase shift capability and 0.8-400MHz operating range. IEEE International Solid-State Circuits Conference, February 1997, pages 332-333.
1996
Signaling interface using current integrating receivers
People:
S. Sidiropoulos and M. Horowitz.
Relevant Papers:
S. Sidiropoulos and M. Horowitz. A 700 Mbps/pin CMOS signalling interface using current integrating receivers. IEEE Journal of Solid-State Circuits, April 1997. S. Sidiropoulos and M. Horowitz. A 700 Mbps/pin CMOS signalling interface using current integrating receivers. VLSI Circuits Symposium, June 1996, pages 142-143.
1994
Synchronous Point-to-Point link interface
People:
S. Sidiropoulos, Chih-Kong Ken Yang, and M. Horowitz.
Relevant Papers:
S. Sidiropoulos, Chih-Kong Ken Yang, and M. Horowitz. A CMOSs 500 Mbps/pin synchronous point to point link interface. VLSI Circuits Symposium, June 1994, pages 43-44.
1992
64k bicmos sram
People:
D. E. Wingard, D. C. Stark, and M. H. Horowitz.
Relevant Papers:
D. E. Wingard, D. C. Stark, and M. H. Horowitz. Circuit techniques for large CSEA SRAMs. IEEE Journal of Solid-State Circuits, June 1992, pages 908-919.
1991
Self Timed Divider rev1 (2um)
People:
Relevant Papers:
Self-timed divider
People:
T. Williams and M. Horowitz.
Relevant Papers:
T. Williams and M. Horowitz. A zero-overhead self-timed 160-nS 54-b CMOS divider. IEEE Journal of Solid-State Circuits, November 1991, pages 1651-1661.T. E. Williams, M. Horowitz. A zero-overhead self-timed 160ns 54b CMOS divider. IEEE International Solid-State Circuits Conference, February 1991, pages 98-99.
Self Timed Divider
People:
Relevant Papers:
1990
Bicmos TLB
People:
L. Tamura, T. Yang, D. Wingard, M. Horowitz, B. Wooley.
Relevant Papers:
L. Tamura, T. Yang, D. Wingard, M. Horowitz, B. Wooley. A 4-ns BiCMOS translation-lookaside buffer. IEEE Journal of Solid-State Circuits, October 1990, pages 1093-1101.
Testarossa : Single Chip Functional Tester
People:
J. Gasbarro and M. Horowitz.
Relevant Papers:
J. Gasbarro and M. Horowitz. A single-chip, functional tester for VLSI circuits. IEEE International Solid-State Circuits Conference, February 1990, pages 84-85.
1989
SPIM
People:
Relevant Papers:
Tester pin electronics
People:
J. Gasbarro and M. Horowitz.
Relevant Papers:
J. Gasbarro and M. Horowitz. Integrated pin electronics for VLSI functional testers. IEEE Journal of Solid-State Circuits, April 1989, pages 331-337.
16 Bit MRC
People:
Relevant Papers:
Spim
People:
M. Santoro and M. Horowitz.
Relevant Papers:
M. Santoro and M. Horowitz. SPIM: A pipelined 64x64b iterative multiplier. IEEE Journal of Solid-State Circuits, April 1989, pages 487-493.M. Santoro and M. Horowitz. A pipelined 64x64b iterative array multiplier. IEEE International Solid-State Circuits Conference, February 1988, pages 36-37.
1988
4k Bicmos Sram
People:
T. Yang, M. Horowitz, B. Wooley.
Relevant Papers:
T. Yang, M. Horowitz, B. Wooley. A 4-ns 4K*1-bit two-port BiCMOS SRAM. IEEE Journal of Solid-State Circuits, October 1988, pages 1030-1040.
1987
Mips-X
People:
M. Horowitz, P. Chow, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, G. Gulak, A. Agarwal, J. Acken.
Relevant Papers:
M. Horowitz, P. Chow, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, G. Gulak, A. Agarwal, J. Acken. MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache. IEEE Journal of Solid-State Circuits, October 1987, pages 790-799. M. Horowitz, J. Hennessy, P. Chow, P. Gulak, J. Acken, A. Agarwal, C. Chu, S. McFarling, S. Przybylski, S. Richardson, A. Salz, R. Simoni, D. Stark, P. Steenkiste, S. Tjiang, M. Wing. A 32 b microprocessor with on-chip 2 Kbyte instruction cache. IEEE International Solid-State Circuits Conference, February 1987, pages 30-31.
Adder
People:
Relevant Papers:
1986
6k sram (3um)
People:
Relevant Papers:
DGR
People:
Relevant Papers:
DGR 2u
People:
Relevant Papers:
SW powersup
People:
Relevant Papers:
dram 2u
People:
Relevant Papers:
Last Updated on Friday, 29 May 2009 09:07